Intelligent ground fault circuit interrupter

ABSTRACT

An intelligent circuit interrupt system is electrically connected between an AC source and a load for interrupting a flow of AC from the source to the load upon detection of an interrupt condition. A circuit interrupter electrically connected to phase and neutral terminals of the AC source defines the interrupt condition. A relay switch with a relay coil and phase and neutral contacts is included such that line and load ends of the phase contact are electrically connected, respectively, between the interrupt means load side phase port and a phase terminal of the load. Line and load ends of the neutral contact are electrically connected, respectively, between the interrupt neutral port and a neutral terminal of the load. The relay coil is electrically coupled between load sides of said phase and neutral contacts for controlling the contacts in response to the interrupt signal. An open-contact miswiring detector (OCMD) is electrically connected to one of the phase and neutral contacts for detecting a miswiring condition when the contacts are in an open state, and a closed-contact miswiring detector (CCMD) is electrically connected to the OCMD and to one of the neutral and phase contacts for detecting a miswiring condition when the contacts are in a closed state. A timing signal generator generates system timing signals. A test circuit electrically coupled to the interrupt means and the timing signal generator tests the interrupt means operability. An alarm circuit is electrically responsive to the test circuit, the timing signal generator, the OCMD and the CCMD for, communicating an open-contact miswiring condition, a closed-contact miswiring condition, an operational failure condition, and a need for external testing condition. A power supply is electrically connected between the load ends of the phase and neutral contacts, and to the timing signal generator.

BACKGROUND OF THE INVENTION

The present invention relates to ground fault circuit interrupters(GFCIs) and, more particularly, to built in test (BIT) circuitry whichincreases operational reliability of GFCI devices.

Ground fault circuit interrupters (GFCIs) were developed to meet a greatneed for a device which is capable of detecting the presence of abnormalcurrent flow, e.g., current flow from a phase line to ground, andimmediately interrupting power to a faulted line in which the abnormalcurrent is detected to protect persons from electric shock, fire andexplosion. To thoroughly protect human life, electric circuit breakersshould detect such faulted currents on the order of 3 to 50 mAcorresponding to load currents ranging on the order of 10 to 100 A.

Prior to GFCI development, differential circuit breakers were known andused in certain European countries to provide ground fault protection.Differential circuit breakers include a differential transformer with acore through which two conductors of the electrical circuit beingmonitored pass. The two wires act essentially as primary windings. Thedifferential transformer also includes current interrupting contacts,which, in the event of a line to ground short circuit or an abnormalleakage current to ground, are forced to a high impedance state, i.e.,an open state. The state of the contacts is controlled by asemiconductor device which is energized by a secondary of thedifferential transformer. It was found that such devices were, however,unacceptable, due to their current sensing insensitivity and, therefore,ineffectiveness in ensuring complete protection for human life.

GFCIs evolved from differential circuit breaker technology. GFCIsdeveloped as ground sensors including a circuit breaker connectedbetween a power source and a load; the power source is connected to theload through the GFCI via a neutral and phase conductor. The GFCI alsoincludes a differential transformer connected across the neutral andphase conductors. The circuit breaker is actuated when the differentialtransformer senses that more current is flowing into the load from thesource through the phase conductor than is flowing back to the sourcethrough the neutral conductor, Primary and secondary windings areincluded within the differential transformer which provides a means forsensing the current. A tertiary winding is disposed proximate theneutral conductor in the vicinity of the load whereby a current isinduced therein in the event of a grounding. If the induced current islarge enough, the circuit breaker contacts are forced open.

Similarly, a ground fault protective system is known which includes adifferential transformer comprised of a toroidal core through which eachof two line conductors and a neutral conductor pass to form primarywindings of at least one: turn. A secondary winding of the differentialtransformer serves as an output winding and is connected to a GFCIcircuit. A trip coil of a circuit breaker having a plurality of contactsin line with the conductors of a distribution circuit is energized witha minimum current. A pulse generator is coupled to the neutral conductorfor producing a high frequency current therein upon grounding of theneutral conductor between the differential transformer and the load. Thehigh frequency current is produced by the periodic firing of a diac whena voltage on a capacitor connected thereto is applied to the outputwinding. The pulses induce voltage pulses in the neutral conductorpassing through the transformer core. The induced voltage pulses do noteffect the current balance in the distribution system as long as theneutral conductor is not grounded on the load side of the transformer.If a grounding occurs, however, the voltage pulses produce a current inthe neutral conductor which does not appear in any of the lineconductors. A consequential imbalance is detected by the ground faultsensing means and causes the contacts to open, interrupting the flow ofcurrent in the distribution system.

Another known arrangement discloses an electric circuit breakerincluding highly sensitive ground fault responsive means. The meansincludes a differential transformer with a toroidal core fabricated of amagnetic material. Phase and neutral conductors pass through an openingin the toroidal core, forming single turn primary windings. Thedifferential transformer also includes a secondary winding comprising aplurality of turns wound on the toroidal core, This secondary winding isconnected to a solenoid assembly comprising an armature, an operatingcoil and a frame mounted on a casing. The armature is adapted formovement between an extended position and a retracted position inresponse to energization of the operating coil. A latch hook is attachedto the armature and disposed for engaging the armature member of theactuator assembly. Thus, energization of the operating coil causes thelatch hook to draw the armature away from a latch member to initiatetripping of the circuit breaker. In consequence, the solenoid assemblyopens the circuit breaker contacts in response to ground fault currenton the order of 3 to 5 mA, and therefore is desirable from thestandpoint of protecting human life against electrical shock.

Another known GFCI comprises a differential transformer connected to anAC source which produces a voltage output when an imbalance in currentflow between the power lines occurs. The voltage output is coupled to adifferential amplifier through a coupling capacitor, rectified, currentlimited and applied to the gate of an SCR. When the SCR conducts, thewinding of a transformer connected across the power line is energized,causing two circuit breaker switches to open. A circuit is also providedfor closing the switch when the line becomes unbalanced.

Another protection arrangement uses a ground leakage protector includinga ground fault release coil controlled by a ground fault detector. Theground fault release coil is normally energized, and is de-energizedwhen a ground fault appears. Upon detection of a ground fault, arestraining latch is disabled resulting in the opening of the circuitbreaker.

Yet another protection arrangement uses a unitary circuit breaker of themolded case type including within its casing means sensitive to groundfaults, means sensitive to overcurrents, and means sensitive to shortcircuit currents. All of the aforementioned means act on a common triplatch of the breaker to cause automatic opening when overcurrent issensed. Also included is a current imbalance detecting foil whichenergizes a tripping solenoid to release a normally latched plunger tocause tripping. Similarly, a ground fault protection system is knownwhich employs a dormant oscillator which is triggered into oscillationto initiate disconnection of the protected distribution circuit uponoccurrence and detection of a neutral to ground type of fault.

While numerous techniques are available for protecting against groundfaults, a key concern in the application of GFCIs in residential andcommercial environments is GFCI reliability. As long as the GFCI isoperating properly, protection is provided against ground faults,preventing electrical shock. In addressing problems of reliability, itmust be considered that most GFCIs are connected to premise electricalwiring at installation and thereafter forgotten, the homeowner orcontractor assuming they will operate correctly one, five or ten yearsafter they are installed. Unfortunately, this is not necessarily so.GFCI devices are subject to a number of failure modes. For example,GFCIs are susceptible to bad power supply, open current sensing coilwinding, integrated circuit failure, shorted or open SCR device, openbreaker coil, failed contacts, etc. Therefore, there exists a need for aGFCI capable of communicating to a user whether or not the device isfunctioning properly any time after installation.

One solution is to incorporate a test button on the face of the GFCIdevice that when pressed simulates a ground fault. This simulated groundfault is treated by the internal circuitry as if a real fault occurred.All internal components and circuitry are thereby exercised and tested.If the internal mechanism of the GFCI is working properly, the contactsopen and power is removed from the electrical circuit protected.Following a test, the GFCI must be reset to its normal operatingcondition. This could be done by pushing a reset button on the face ofthe GFCI device. Users would be instructed to test their GFCIsperiodically and replace failed devices. The problem with this scheme isthat in reality most users do not test their GFCIs on a regular basis ifat all, even when the face of the GFCI is labeled with the words `TESTMONTHLY` on its face. Thus, there is a real need for a GFCI device thatincorporates the ability to automatically test itself periodicallywithout any user intervention, in addition to reminding the user toperiodically test the GFCI manually.

One factor that lowers GFCI reliability, in addition to a user's failingto test the GFCI, is a power outage and the corresponding surge whenpower is restored. Therefore it would be beneficial for the GFCI todetect power being restored after a sufficiently long power outage andto force the user to subsequently test the device. Power restorationcould cause huge spikes of voltage and current to appear on the powerline thus creating a possibility of component failure.

Another potential problem arises because GFCIs typically installed priorto the electricity being applied, especially in new construction.Consequently, there is a real possibility that an installer mightinadvertently connect the line side of the AC wiring to the load side ofthe GFCI. While downstream electrical devices are protected, anyreceptacles built into the GFCI device itself would not be protected;creating a potential hazard. The GFCI then would remain wiredincorrectly unless the device was able to detect a miswiring condition.The ability to detect whether line and load sides were reverse wiredwould increase the safety level of the device. At the time power isinitially applied, the GFCI would alert the user by way of a visualand/or audible alarm, in the event a miswiring condition was detected.The visual and/or audible alarm could not be eliminated until themiswiring condition was removed decreasing the probability of incorrectwiring.

OBJECTS AND SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide anintelligent ground fault circuit interrupter (IGFCI) device that canautomatically test its internal circuitry on a periodic basis, therebyboosting its own probability of proper operation in the event of a realground fault. Such a GFCI could test itself on a monthly, weekly, dailyor even hourly basis. In particular, all key components could be testedexcept for the relay contacts. This is because tripping the contacts fortesting would have the undesirable result of removing power to theuser's circuit. However, once a month, for example, the GFCI devicecould generate a visual and/or audible signal or alarm reminding theuser to manually test the GFCI. The user would, in response to thesignal, initiate a test by pushing a test button, thereby testing theoperation of the contacts in addition to the rest of the GFCI circuitry.Following a successful test, the user would reset the GFCI device bypushing a reset button.

Another object of the present invention to provide an intelligent groundfault circuit interrupter (IGFCI) system which delivers increasedreliability of operation over conventional GFCIs. The IGFCI incorporatesBIT circuitry and partial redundancy in an effort to deliver suchincreased reliability. The BIT circuitry automatically tests internalGFCI components except relay contacts on a periodic basis, such as oncean hour. If a failure is detected, a visual and/or audible alarm isgenerated. The relays are opened immediately in consequence using builtin redundant relay trip means.

Another object of the invention is to provide an IGFCI with the abilityto detect when the GFCI is incorrectly wired in an electrical wiringsystem, e.g., when load and line connections have been reversed. Upondetection of a miswiring condition, a visual and/or audible alarm istriggered to alert the user that the device is in an incorrectly wiredstate, and the relay contacts are opened removing AC power fromdownstream electrical devices. The GFCI can not be reset unless themiswiring condition is removed.

Another object of the present invention is to provide an IGFCI with theability to monitor the steady or slowly rising ground leakage currentpresent on the AC power line and adjust the trip threshold of theinternal GFCI circuit accordingly up or down, preventing nuisancetripping of the GFCI. The trip threshold of the GFCI would track slowlyrising and falling ground leakage currents caused by certain appliances.However, 5 ma of fast rising leakage current would immediately cause theGFCI circuit to trip the relay and open the contacts.

Yet another object of the present invention is to provide a periodictest reminder signal to alert a user to manually test the IGFCI device.A visual and/or audible alert signal would be generated 30 days afterpower was initially applied or 30 days after the last manual test wasperformed. A daylight detector would preferably be included to silencethe test reminder signal during the evening and nighttime hours whilemost people are asleep.

The present invention provides an intelligent circuit interrupt systemfor electrical connection between an AC source and a load forinterrupting a flow of AC between the source and load upon detection ofan interrupt condition. The system includes a circuit interrupterelectrically connected to phase and neutral terminals of the AC sourcefor cutting off the AC at the source at detection of the interruptcondition. The circuit interrupter acts in conjunction with a relayswitch which includes a relay coil and phase and neutral contacts. Phaseand load ends of the phase contact are electrically connected,respectively, to a load side phase port of the interrupt means and aload phase terminal. Phase and load ends of the neutral contact areelectrically connected, respectively, to a load side neutral port of theinterrupt means and a load neutral terminal. The relay coil controls thestate of the contacts (i.e., high or low impedance state) in response toan interrupt signal generated in the interrupter.

The system includes an open-contact miswiring detector (OCMD)electrically connected to one of the phase and neutral contacts fordetecting a miswiring condition when the contacts are in an open state,and a closed-contact miswiring detector (CCMD) electrically connected tothe OCMD and to one of the neutral and phase contacts for detecting amiswiring condition when the contacts are in a closed state. The systemalso includes a timing signal generator for generating system timingsignals, a test circuit electrically coupled to the interrupt means andthe timing signal generator for testing interrupt means' operability andgenerating a signal therefrom, an alarm circuit electrically responsiveto the test circuit, the timing signal generator, the OCMD and the CCMDfor communicating an open-contact miswiring condition, a closed-contactmiswiring condition, an operational failure condition, and a need forexternal testing condition, and a power supply electrically connectedbetween the load ends of the phase and neutral contacts, and to thetiming signal generator.

Preferably, the various objects and features of the invention will beapparent from the following description in which the preferredembodiments are set forth in detail in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a preferred embodiment of thepresent invention;

FIG. 2 is a detailed schematic diagram of a power supply circuit whichmay be utilized within the embodiment of FIG. 1;

FIG. 3 is a detailed schematic diagram of an audible alarm circuit whichmay be utilized within the embodiment of FIG. 1;

FIG. 4 is a detailed schematic diagram of a timing signal generatorwhich may be utilized within the embodiment of FIG. 1;

FIG. 5 is a detailed schematic diagram of an open-contact miswiringdetector which may be utilized within the embodiment of FIG. 1;

FIG. 6 is a detailed schematic diagram of a closed-contact miswiringdetector which may be utilized within the embodiment of FIG. 1;

FIG. 7 is a detailed schematic diagram of the ground fault circuitinterrupter which may be utilized within the embodiment of FIG. 1;

FIG. 8 is a detailed schematic diagram of an automatic gain controlcircuit which may be utilized within the embodiment of FIG. 1;

FIG. 9A is a detailed schematic diagram of a portion of self testcircuitry which may be utilized within the embodiment of FIG. 1; and

FIG. 9B is a detailed schematic diagram of a portion of the self testcircuitry which may be utilized within the embodiment of FIG. 1;

DETAILED DESCRIPTION OF THE INVENTION

A preferred embodiment of an Intelligent Ground Fault CircuitInterrupter (IGFCI) System 10 (hereinafter referred to interchangeablyas "IGFCI", "system" and "device") of the present invention will now bedescribed in accordance with FIG. 1. The IGFCI 10 shown thereinpreferably includes a standard Ground Fault Circuit Interrupter (GFCI)12 as its "core" structure, readily known to those skilled in the art, aself test circuit 14, open-contact and closed-contact miswiringdetectors 20, 24, an alarm circuit 18 and an automatic gain controlcircuit 16. Installed properly, the system 10 protects all downstreamelectrical devices connected to it as well as any receptacles present inthe device itself. It should be noted, however, that the description ofthe preferred embodiment is presented merely for illustration purposesonly and is not meant to limit the scope or spirit of this invention.

FIG. 1 shows the IGFCI 10 as a four terminal device which includes powerinput terminals AC-1 and AC-2, referred to hereinafter as phase andneutral line terminals, and system output terminals LOAD-1 and LOAD-2,referred to hereinafter as phase and neutral load terminals. An AC powersource (not shown in the figure) is connectable to the device 10 toprovide AC power therein via phase and neutral line terminals AC-1 andAC-2. A metal oxide varistor (MOV) 270 is shown electrically connectedbetween phase and neutral line terminals for suppressing voltage spikes.The GFCI 12 is disposed in a current path for alternating current flowfrom the AC source to the load. The GFCI includes line (AC-1₋₋ IN,AC-2₋₋ IN) and load side (AC-1₋₋ OUT, AC-2₋₋ OUT) phase and neutralports, wherein AC-1₋₋ IN and AC-2₋₋ IN electrically connect the GFCI tophase and neutral line terminals of the AC source. The GFCI is alsoelectrically connected to a self-test circuit 14, a first contact 28 ofa relay switch 31 at terminal AC-1₋₋ OUT and to a second relay contact30 of switch 31 at neutral line terminal AC-2₋₋ OUT.

Also connected to the line side of relay contact 28 is a phase port ofthe open-contact miswiring detector (OCMD) 20, a load port of which iselectrically connected to the load side of relay contact 28, phase loadterminal LOAD-1 of the IGFCI and a phase port of the CCMD. Theclosed-contact miswiring detector (CCMD) 24 is electrically connected ata line side phase port to both GFCI load side neutral terminal AC-2₋₋ INand to a line side of relay contact 30, and at a load side neutral portto both a load side of relay contact 30 and IGFCI load side neutralterminal LOAD-2.

The IGFCI 10 also includes a power supply 26 which provides DC for theIGFCI from the AC source. A phase port of power supply 26 iselectrically connected to phase load terminal LOAD-1 and the load sideof relay contact 28. A neutral port of the power supply is electricallyconnected to neutral load terminal LOAD-2, and the load side of relaycontact 30. The power supply generates and supplies DC to the system(i.e., Vcc and Vcc/2, which are not shown in the system diagram of FIG.1). A frequency calibration signal port is electrically connected to aninput port of a timing signal generator 22. Timing signal generator 22is electrically connected to timing ports of open and closed miswiringcontact detectors 20, 24, to self test circuit 14 and to alarm circuit18, respectively. Alarm circuit 18 is also electrically connected toself test circuit 14, open-contact miswiring detector 20 andclosed-contact miswiring detector 24.

One of the key features of the IGFCI 10 is the device's ability todetect improper installation, i.e., miswiring, to an electrical wiringsystem in which it is installed. The most common cause of miswiringoccurs when the AC power source is connected to the LOAD-1, LOAD-2terminals and the load is connected to the AC-1, AC-2 terminals. Thepresent invention anticipates such miswirings whether the contacts areopen or closed. More particularly, the open-contact miswiring detector20 detects a miswiring condition when relay contacts 28, 30 are in anopen state, and the closed-contact miswiring detector 24 detectsmiswiring when the relay contacts are in a closed state.

Relay contacts 28, 30 pass AC to the load if the GFCI 12 maintains thecontacts in a closed state. Automatic Gain Control circuit (AGC) 16continually adjusts the sensitivity of the GFCI to track or compensatefor ground leakage current typically generated by loads attached to thesystem, i.e., appliances such as refrigerators, dishwashers, washingmachines, etc. The ground leakage current in many such appliances cancause nuisance tripping of GFCIs if the appliances are located on ashared branch circuit, such as the GFCI, due to the design of electricalcircuitry contained therein. Accordingly, the IGFCI, through theautomatic gain control current, recognizes and adjusts for this type ofleakage current. The self test circuit 14 interfaces with portions ofthe GFCI core circuitry to provide for unaided, unattended self testingof the entire GFCI circuit including its SCR and trip coil.

Power supply 26 generates the DC electrical voltages needed by theinternal circuitry of the device 10 via DC connections identified inFIGS. 2-8, 9A and 9B, and includes phase, neutral and frequencycalibration (i.e., 60 HZ, to be discussed in greater detail below)ports. The device 10 utilizes voltages of 12 and 6 volts, i.e., Vcc and1/2 Vcc, respectively. Timing signal generator 22 generates the signalswhich ultimately alert the user of a need to test the device 10, as wellas triggering periodic internal self tests. The alarm circuit 18 ismeant to indicate an alarm state to a user, for example, an audiblesignal to communicate various alerts to a user such as when a miswiringsituation exists. In the preferred embodiment, the alarm circuitincludes a ceramic piezo element as the sound producing component thatactually generates the alarm sound. As an alternative, sound may beproduced by a speaker, buzzer or other sound generating element known tothose skilled in the art. Alternatively, it is envisioned that the alarmcircuit generates a flag signal which may be transmitted to a sensorlinked to a digital computer, which acts accordingly.

The circuits which define the embodiment of the present invention shownin FIG. 1 and briefly described above will now be explained in greaterdetail with reference to FIGS. 2-8, 9A and 9B. In the figures, likenumerals will define like terms.

FIG. 2 is a detailed schematic diagram of one embodiment of power supply26, previously identified in FIG. 1. Power supply 26 is shownelectrically connected at its phase port to the load side of relaycontact 28 and terminal LOAD-1; the frequency calibration port outputs azero crossing, or clock, signal "60 HZ" which is generated therein tosynchronize system or device 10 operation. The power supply rectifies ACsupplied through the GFCI 12 across contact 28 while operational,thereby providing a 1/2 Vcc signal and a Vcc signal to the rest of thesystem. The power supply is preferably a CMOS device in order tominimize total power dissipation for the device 10 averages between 10to 20 milliwatts.

A preferred form of the power supply circuit is as follows. A resistor32, having a nominal value of between 10 and 20 ohms, is electricallyconnected at a first end to the load end side of relay contact 28 and ata second end to both a first end of a capacitor 36 and a first end of aresistor 34. Second ends of resistor 34 and capacitor 36 areelectrically connected to the timing signal generator 22, as mentionedabove, to a cathode end of a zener diode 38 and to an anode end of adiode 40. Capacitor 36 serves as a series impedance to reduce the ACline voltage at the load end side of contact 28 when the powerrequirement on the supply is relatively low; capacitor 36 also aids inpower factor correction. By defining capacitor 36 with a 1 μF value, anequivalent impedance of approximately 2.6 KΩ is generated at 60 Hz.Resistor 34, in parallel with capacitor 36, is designed with a highvalue (around 100K ohms) to limit the current through the zener diode38. Zener diode 38 displays a breakdown value of approximately 15 V inorder to pre-regulate the incoming AC voltage. The zener diode 38 alsodefines the origin of the zero crossing signal, 60 HZ, the clock inputto timing signal generator 22.

Cathode end of diode 40 is electrically connected to an anode end of astorage capacitor 42, a first end of a current-limiting resistor 44, andcollectors of NPN transistors 50, 48, 58. Diode 40 provides half-waverectification for storage capacitor 42, which supplies current to zenerdiode 46 and prevents the discharge of storage capacitor 42 during thenegative half cycle of the AC source. A second end of resistor 44 iselectrically connected to both a base of transistor 48 and a cathode endof a second zener diode 46. Resistor 44 supplies current from storagecapacitor 42 for zener diode 46, which displays a breakdown voltage of13 V to maintain a constant voltage at NPN transistors 48, 50. Anodeends of zener diodes 38, 46 and cathode end of storage capacitor 42 areelectrically connected to ground.

An emitter of transistor 48 is connected to a base of transistor 50, andan emitter of transistor 50 is connected to a collector of an NPNtransistor 60 (defining Vcc). An emitter of transistor 58 iselectrically connected to a base of transistor 60, an emitter of whichprovides 1/2 Vcc. A collector of transistor 60 is electrically connectedto a first end of a resistor 54, a first end of a storage capacitor 56and a base of transistor 58. Cathode end of storage capacitor 56 andsecond end of resistor 54 are electrically connected to ground. Storagecapacitor 56 helps to maintain the base of transistor 59 at a constantvoltage in the event transients appear on Vcc. Resistors 52, 54, aredefined to be approximately 100 KΩ to form a voltage divider whoseoutput is approximately one half the Vcc voltage for regulating the NPNtransistor pair 58, 60. Consequently, a constant voltage ofapproximately 1/2 Vcc is supplied from the emitter of transistor 60. Thereduced 1/2 Vcc voltage serves as a reference voltage for some of thevoltage comparators used in the circuitry of device 10. Because powersupply 26 is connected to the AC source on the load side of relay 28, nopower is provided to the system the relays 28, 30 trip for any reason.

FIG. 3 is a detailed schematic diagram of one embodiment of an alarmcircuit 18, previously identified in FIG. 1. The alarm circuit 18receives several inputs from circuits which have yet to be described indetail, for example, a MISWIRE₋₋ OPEN bar signal is supplied fromopen-contact miswiring detector 20 (FIG. 5), a MISWIRE₋₋ CLOSED barsignal from closed-contact miswiring detector 24 (FIG. 6), and a pair ofSCR₋₋ FAIL bar and GFCI₋₋ FAIL bar signals from self-test circuit 14(FIGS. 9A, 9B), all of which are supplied to a Nand circuit 62. The`bar` designation after any signal name signifies that the signal isactive low. The logical output of Nand circuit 62 provides an ALARM₋₋TRIP signal to cathode ends of diodes 64 and 66. An anode end of diode64 is electrically connected to a first end of a resistor 65 to generatean input signal to a Nand circuit 70. Vcc is also connected to thesecond end of resistor 65 and logical Nand circuit 70. The logicaloutput of Nand circuit 70 is provided to a cathode end of a diode 80, ananode end of diode 66, and to first ends of resistors 72 and 76. Secondend of resistor 76 is electrically connected to a cathode end of diode74, the anode end of which is electrically connected to a first end of adischarge capacitor 78, a second end of resistor 72 and a second inputto Nand circuit 70.

An anode end of diode 80 is electrically connected to Vcc through aresistor 82 and to an input of a logical Or circuit 84. A second inputto Or circuit 84 receives a TEST₋₋ REMINDER signal from the timingsignal generator 22 (to be described below with reference to FIG. 4);the Or circuit logical output is electrically connected to a logicalNand circuit 86. A second input to Nand circuit 86 is electricallyconnected to the circuit's logical output through a resistor 88. Themagnitude of the output (feedback) signal is held on a first end of acapacitor 90, the second end of which is grounded. The logical output ofNand circuit 86 is also electrically connected to an input to PIEZOelement 92, an output of which is connected to ground, to generate analarm. The PIEZO element is just one example of alarm or soundgeneration circuitry 18 which may be utilized in the system to producevarious duration beeping or alarm sounds to communicate when the system10 is in certain states, or at the occurrence of various events. Forexample, the alarm or beeping would signal a user in the event amiswiring condition were detected.

The actual frequency of the sound emitted by the circuit 18 isdetermined by the values of resistor 88 and capacitor 90, which arecoupled to gate 86 in a classic oscillator configuration. The charge anddischarge of capacitor 90 causes the Nand circuit 86 logical output toswing back and forth or oscillate with a duty cycle of approximately 50%because capacitor 90 is charged and discharged through the same resistor88. If, however, the output of Or circuit 84 goes low, oscillationscease because the output of Nand circuit 86 remains high no matter whatappears across capacitor 90. Preferably, resistor 88 and capacitor 90define an RC time constant which rings sound producing component 92 atbetween 2.5 to 3.0 KHz. As long as the output of OR gate (circuit) 84 ishigh, the oscillator causes the resonator 92 to generate a tone.

Nand circuit 70, resistors 72, 76, diode 74 and capacitor 78 determinethe duty cycle (i.e., the turn on and turn off times) of the oscillatorbuilt around Nand circuit 86 to drive PIEZO element 92. The duty cycleof the tone, however, is not symmetrical because resistors 72, 76 havedifferent values, the parallel combination of which determines the offduration of the tone. Due to the blocking effect of diode 74, resistor72 alone determines the on duration of the tone. Resistors 72, 76 arepreferably chosen to produce an approximately 150 millisecond tone-onand one second tone-off periods. Tone is produced when the ALARM₋₋ TRIPsignal is high (i.e., diodes 64, 66 are reverse biased). This allows theoutput of logical Nand circuit 70 to oscillate due to the charge anddischarge of capacitor 78, similar to the action of capacitor 90 asdiscussed above.

The alarm signals input at logical Nand circuit 62 are generated by thesystem 10 when either a miswiring condition or a GFCI related failure isdetected. A low, therefore, at any of these inputs causes the alarmcircuitry 18 to output an auto or visual alarm to alert a user that amiswiring condition or failure has occurred. Conversely, keeping thetone or alarm indicia off, the non-feedback inputs to logical Nandcircuits 70, 86 are held in the low state by the ALARM₋₋ TRIP signal,causing the logical signals output therefrom to remain in the high statewhich prevents oscillation. A low output from Nand circuit 62 isprovided through diodes 64, 66 compelling the outputs of Nand circuits70, 86 to remain in the high state. Logical Nor circuit 84 enables theoscillator driving the PIEZO element 92 with the TEST₋₋ REMINDER signalgenerated within the timing signal generator 22. This TEST₋₋ REMINDERsignal functions to remind a user to periodically manually test thedevice 10. When the TEST₋₋ REMINDER signal is high, the resonator 92will produce a short alarm tone (or short infrared of visible lightoutput) once per minute.

FIG. 4 is a detailed circuit diagram of one embodiment of a timingsignal generator 22 described above in relation to FIG. 1. Thecombination timing signal generator and alarm circuit 18 containedwithin the present invention was developed in part because it was foundthat user instructions (accompanying conventional GFCIs) forperiodically testing the system or device at least once per month aretypically ignored by the user. Further, most users are found to ignorethe clear notices placed not only within the unit's installationinstructions but even those on the face of the device itself. The timingsignal generator attempts to compensate for this reality by causing tobe generated a short chirping sound once every minute to remind a userto test the device once a test reminder signal is enabled (preferablyevery 30 days).

The timing signal generator 22 also generates test pulses used by builtin test circuitry (self-test circuit 14 identified as FIGS. 9A, 9B, tobe discussed in detail below) to precipitate automatic self-testing onceevery hour, and the power on reset signal (PWR₋₋ ON₋₋ RESET) which isused by the system 10 to put various components in a known state whensystem power is initialized. At the core of the signal generator 22 is atimer circuit 114, which may embody any monolithic integrated circuit,group of MSI or LSI logic functions, ROM based sequencer or other clockdriven circuit known to those skilled in the art that is capable ofcounting. Upon application of system power, the timer 114 generatesPWR₋₋ ON₋₋ RESET and PWR₋₋ ON₋₋ RESET bar signals, which are activeimmediately after power is applied and are active for at least 100 msec.The 60 HZ signal provided by the power supply 26 (zero crossing signalgenerated across the zener diode 38) drives the timer. All the signalsgenerated by the timer 114 are derived ultimately from this clock input.

As mentioned above, 30 days after AC power is initially applied, theIGFCI device 10 emits an active high test reminder signal, TEST₋₋REMINDER, to alert a user of a need to manually test the device 10. Todo so, the user presses a momentary switch button 94 (not shown inFIG. 1) located on the face of the device 10, one end of which isconnected to the LOAD-1 terminal. An opposite end of switch 94 iselectrically connected to a first end of a resistor 96, a second end ofwhich is connected to terminal AC-2. The first end of resistor 96 isalso electrically connected to a first end of a resistor 98, a secondend of which is connected to an anode end of a diode 100. A cathode endof diode 100 is electrically connected to a first end of a resistor 102,an anode end of a diode 106, a reset input to timer 114, and a first endof a resistor 112. A second end of resistor 112 is electricallyconnected to a first end of a capacitor 113, a second end of which isconnected to ground, and also as a GND input to timer 114. Cathode endof diode 106 is electrically connected to Vcc and an anode end of adiode 108. A cathode end of diode 108 is electrically connected to afirst end of a capacitor 110, a second end of which is connected toground, and as a Vdd input to timer 114.

In addition to the POWER₋₋ ON₋₋ RESET, POWER₋₋ ON₋₋ RESET bar signalsmentioned above, the timer also generates 150 MS, 300 MS, 1 MIN, 1 HR, 2HR, 60₋₋ DAY, 120₋₋ DAY and 240₋₋ DAY signals. Signals 60₋₋ DAY, 120₋₋DAY and 240₋₋ DAY are provided as inputs to a logical Or circuit 146, anoutput of which is provided to a logical Nand circuit 126 along with the1 MIN and DAY signals generated by a DAY signal generator circuit 117.Within the DAY signal generator circuit 117, a first end of a resistor120 is electrically connected to an anode end of a diode 124. Second endof resistor 120 is electrically connected to first ends of a resistor116, and a photoresistor 118, which are electrically connected inparallel to Vcc. Second ends of resistors 116 and 118 are electricallyconnected to a base and emitter of an NPN transistor 119, respectively.An emitter transistor 119 is electrically connected to a first end of aresistor 122, a second end of which is grounded, and to a cathode end ofa diode 124.

The PWR₋₋ ON₋₋ RESET bar is provided to each of three logical Orcircuits 128, 130 and 132. 150 MS is provided to logical Or circuits 130and 132, and 300MS is provided to logical Or circuit 128. The output oflogical Or circuit 128 is provided as an active-low reset to a D-typelatch circuit 134. An output from logical Nand circuit 126 is providedas a clock input to the latch circuit; Vcc holds the circuit's "D" inputhigh through a resistor 140. Also included are "D" type latch circuits136 and 137, which are electrically connected via pull-up resistors 142and 144 to Vcc. The 1 HR and 2 HR signals are electrically connected asclock inputs to the f/f circuits 136 and 138, respectively from thetimer 114. Signals output from logical Or circuits 130 and 132 areelectrically connected to the f/f circuits 136, 138 as active low resetinputs. Finally, TEST₋₋ REMINDER, 1 HR₋₋ PULSE bar and 2 HR₋₋ PULSE barsignals are the logical outputs emanating from the "Q", "Q bar" and "Qbar" outputs of latch circuits 134, 136 and 138, respectively.

Actuation of momentary switch 94 simulates a ground fault by momentarilycausing the current flowing into the device via terminals AC-1 and AC-2to differ. If working properly, the GFCI circuit 12 (FIG. 7) detects thecurrent-flow difference via magnetic cores 312, 314, and generates anSCR control signal thereby. As a result, the SCR 244 within the GFCI istriggered, the relay trip coil 260 is energized and the relay contacts28, 30 of the IGFCI are exercised. Pressing the test button 94 alsocauses the timer 114 to reset by resetting its internal counters andbeginning again a count of a 30 day period. The timer's reset input,which is active high, is coupled to the TEST₋₋ BUTTON signal throughresistor 98 and diode 100. Resistor 102 and capacitor 104 providefiltering for the reset input signal.

The "D" latch circuit 134, therefore, operates as a one-shot andgenerates a 150 ms long high pulse once every minute, i.e., the TEST₋₋REMINDER signal. Since its input is pulled high through resistor 140 toVcc on each rising edge of its clock input, a logical high is clocked into the latch circuit and appears at the circuit's "Q" output. The outputof logical Nand circuit 126 goes high when all its inputs are high.Approximately 30 days after power is initially applied to the device 10,the 60₋₋ DAY signal goes high causing the output of logical OR circuit146 to go high. If the DAY signal and the 1 MIN signals also go high,latch ("D" f/f) circuit 134 gets clocked and a logical high appears atthe circuit's "Q" output. Approximately 150 ms later, the 300 MS signalfrom timer 114 goes low and resets the latch circuit 134 "Q" output to alogical low. The 300 MS signal is gated with the PWR₋₋ ON₋₋ RESET barsignal to allow either signal to reset the latch circuit 134. This resetsignal can also reset latch circuits 136, 138 through logical Orcircuits 130, 132 respectively.

The DAY signal output from circuit 117 is driven high when the intensityof the light surrounding the IGFCI device 10 sufficiently lowers theresistance of photoresistor 118. Consequently, increased current flowsthrough the emitter of transistor 119 and resistor 122, reverse biasingdiode 124 and the voltage level of the DAY signal to be pulled up toVcc. When there is insufficient light intensity (i.e., at night), theresistance of photoresistor 118 is very high which limits current flowthrough resistor 122 to reverse bias diode 124. Resistor 122 then sinkscurrent to ground keeping the output of Nand circuit 126 a logical low.This prevents the TEST₋₋ REMINDER signal from sounding during theevening and night hours the time most people are asleep. If the userfails to heed the once a minute TEST₋₋ REMINDER signal, commenced after30 days, the signal will remain active for approximately another 210days after which the timer 114 resets itself. If at any time during the210 days the user manually tests the device 10, the timer 114 resets andbegins again counting the 30 day period again. The 120₋₋ DAY, 240₋₋ DAYclock signals are ORed with the 60₋₋ DAY in logical Or circuit 146 toform one of the three inputs to logical Or circuit 126, each of whichmay cause a change of state in the latch circuit 134 output, i.e., theTEST₋₋ REMINDER signal.

Another key feature of the IGFCI system 10 is its ability to detect amiswiring condition when the system is wired with the contacts ofcontact relays 28, 30 in either an open or closed state. This is veryimportant because it is impossible to predict what state the relaycontacts will be in when AC power is first applied. Open-contactmiswiring detector 20 detects and memorizes, using latch circuit 174,whether the AC power is wired correctly to the AC-1, AC-2 terminals, orincorrectly to the LOAD-1, LOAD-2 terminals. This detection takes placeat a point in time shortly after power is initially applied. If thedevice 10 is installed with the relay switches 28, 30 already in theclosed position, which is a real possibility, the detection circuitry 20defaults, in which case a determination of proper or improper wiringmust be made by the closed-contact miswiring detector 24.

A detailed circuit diagram a preferred form of an open-contact miswiringdetector 20 will now be described with reference to FIG. 5. AC-1₋₋ INterminal is shown in the figure electrically connected to an anode endof diode 148 and line side end of contact 28; the load side end ofcontact 28 is electrically connected to both the LOAD₋₋ 1 terminal andan anode end of a diode 160. Cathode ends of diodes 148, 160 areelectrically connected to first ends of resistors 150, and 162,respectively. Second ends of resistors 150 and 162 are connected tofirst ends of resistors 152, 164, respectively, and also to a base ofNPN transistors 156 and 168, respectively. Emitters of transistors 156,162 are grounded and collectors are connected through resistors 154,156, respectively, to Vcc. A second end of resistor 152 is connected toterminal AC-2₋₋ OUT, the line side end of contact 30, a first end of aresistor 151 and a first end of a capacitor 153. Accordingly, resistorcombination 150, 152 acts as a voltage divider to bias the base oftransistor 156.

The collector of transistor 156 also is electrically connected to both alogical Or circuit 175 and a logical And circuit 172. A second end ofresistor 164 is electrically connected to load side end of relay contact30, a second end of resistor 151 and a second end of capacitor 153.Resistor combination 162, 164 together form a voltage divider whichdefines the base input to transistor 168. The collector of transistor168 also is electrically connected to Or circuit 175 and as dual inputsto a logical Nand circuit 170. An output of Nand circuit 170 is providedas a logical input to And circuit 172. An output of And circuit 172 isprovided as a "D" input to a latch circuit 174.

The functioning of detector circuit 20 is dependent upon NPN transistors156, 168, which are arranged to detect AC power between the AC line sideand LOAD terminals. If an AC power source is correctly wired to theterminals AC-1, AC-2, and, if the contacts of relays 28, 30 are in theopen position, AC power is applied only across diode 148. The LOAD sideof the relays 28, 30 are left without AC power. Collector current flowsthrough resistor 154 from Vcc to ground and a logic low is applied tothe input of logical And circuit 172. Accordingly, the input to latchcircuit 174 is a logical low regardless of the state of transistor 168as long as AC power is applied across terminals AC-1, AC-2. Timingsignal generator 22 (FIG. 4) supplies the PWR₋₋ ON₋₋ RESET bar signal asa clock input to latch circuit 174, the leading edge of which clocks the"low" input out as a "Q bar" signal defining a MISWIRE₋₋ OPEN bar signalin a high state (i.e., no miswiring condition). Therefore, if power isapplied with the contacts 28, 30 open, the output signal from thedetection circuitry 20 remains high.

Alternatively, if AC power is wired incorrectly to the LOAD-1, LOAD-2terminals, and the relay contacts 28, 30 are in the open position,transistor 156 remains off and resistor 154 pulls one input to Andcircuit 72 logically high upon the application of AC power. Currenttherefore flows through diode 160 and is divided within a voltagedivider formed by resistors 162, 164, turning on transistor 168. Inconsequence, current flows through resistor 166, grounding the inputs tological Or circuit 170. The Or circuit logical output goes high whichcauses the signal output from latch circuit 174, MISWIRE₋₋ OPEN, to golow upon the rising edge of the PWR₋₋ ON₋₋ RESET bar signal. A lowMISWIRE₋₋ OPEN bar signal triggers the alarm circuitry 18 which alertsthe user that a miswiring condition exists. Since timer 114 of timingsignal generator 22 is synchronized to the 60 HZ signal, the rising edgeof the PWR₋₋ ON₋₋ RESET bar signal does not occur at a zero crossing butat a point within the AC cycle at which the data operating as logicalinputs to Nand and And circuits 170, 172, are reliable.

If AC power is incorrectly wired to the LOAD-1, LOAD-2 terminals, andrelay contacts 28, 30 are closed, application of AC power will preventthe open-contact miswiring detector 20 from triggering the alarm. TheMISWIRE₋₋ OPEN bar output signal therefore remains high. Consequently,deference is made to closed-contact miswiring detector 24 fordetermining whether the device 10 is wired correctly and logical Orcircuit 175 generates a CONTACT₋₋ CLOSED bar signal from the collectoroutputs of transistors 156, 168, which are low only when relay contacts28, 30 are in the closed state. Closed-contact miswiring detector 24utilizes the CONTACT CLOSED bar signal to determine whether the GFCIcircuitry 12 is properly wired. If the relay contacts 28, 30 are open,control passes from the closed-contact miswiring detector 24 to theopen-contact miswiring detector 20 for the determination whether thedevice 10 is wired properly.

Referring now to FIG. 6, a preferred form of the closed-contactmiswiring detector 24 described above with reference to FIG. 1 will bedescribed. Because mechanical relay contacts 28, 30 exhibit a finiteohmic resistance, a detectable voltage drop is generated across each atpower up when the contacts are in their closed state. More particularly,upon system power-up, the system 10 simulates a load which draws 2 to 3amps on the load end sides of contacts 28, 30 for a time period ofapproximately 250 μsec. This burst of current generates a finite voltagedrop across the equivalent impedance of the relay contacts 28, 30, whichis on the order of 3 mΩ. This voltage drop can be detected and amplifiedusing standard components and will only be generated if the device 10 iswired correctly. If it is improperly wired, no voltage drop will appearacross the relay contacts. In the preferred embodiment, the voltage dropacross only one of the relay contacts, relay contact 28, is detected.However, either relay contact 28, 30 could be used to detect thepresence of the voltage developed across its equivalent "on" impedance.

Line side end of contact 28 is electrically connected to terminal AC-1₋₋OUT of GFCI 12 and first ends of resistors 182, 184, and a capacitor186. A second end of resistors 182, 184 and a first end of capacitor 188are electrically connected to the load end side of relay contact 28 andto terminal LOAD-1. Second end of capacitors 186, 188 are electricallyconnected, respectively, to inverting and non-inverting inputs of op-amp190. The inverting input to op-amp 190 is also electrically connected toa cathode end of a diode 189, an anode end of a diode 187 and a firstend of a resistor 181. The non-inverting input to op-amp 190 also iselectrically connected to an anode end of diode 189, a cathode end ofdiode 187 and a first end of a resistor 183. Second ends of resistors181, 183 are connected respectively to a first end of resistor 178 and asecond end of resistor 176, and, a second end of resistor 178 and afirst end of resistor 180. First end of resistor 176 is connected to Vccand second end of resistor 180 is grounded. An output of op-amp 190, aCONTACT₋₋ CURRENT signal, is electrically connected a logical Or circuit207.

Also electrically connected to terminal LOAD-1 is an anode end of adiode 202; a cathode end of diode 202 is electrically connected to firstends of resistors 204 and 192. Second ends of resistors 204 and 192 areeach electrically connected to a drain of FET 206 and an anode end ofdiode 196. A cathode end of diode 194 is electrically connected to botha first end of a resistor 196, a second end of which is connected toterminal LOAD-2, and a base of an NPN transistor 200. An emitter oftransistor 200 also connects to terminal LOAD-2, while its collector(CURRENT₋₋ FLOW signal) electrically connects to a gate of FET 206, afirst end of a resistor 198, and an input to a Nand circuit 208. ThePWR₋₋ ON₋₋ RESET signal, generated by timer 114 within timing signalgenerator 22 is provided to a second end of resistor 198 to control thestate of the gate of FET 206.

The CONTACT₋₋ CLOSED bar signal, generated within the open-contactmiswiring detector 20 is input to Or circuit 207 with the CONTACT₋₋CURRENT signal. An output of Or circuit 207 is provided as a "D" inputto a latch circuit 212. The CURRENT₋₋ FLOW signal is provided into Nandcircuit 208, an output of which (CURRENT₋₋ FLOW bar), with the PWR₋₋ON₋₋ RESET bar signal, are provided as a clock input to the latchcircuit 212 via logical Or circuit 210. A "Q" latch circuit outputdefines a MISWIRE₋₋ CLOSED bar signal. Upon device power-up, a positivegoing PWR₋₋ ON₋₋ RESET pulse is provided by timer 114 as an Or circuit210 input, to the collector of transistor 200 and to the gate ofn-channel MOSFET 206 through resistor 198 (100 Kohms). The PWR₋₋ ON₋₋RESET signal has a minimum duration of at least one complete AC cycle.The time length of the pulse is defined to overlap at least onenegative-to-positive-going zero crossing of a power signal generated bythe AC power source. MOSFET 206 is used as a voltage controlled switchto control the flow of current from the AC power source through resistor204. Having a value of approximately 1-2 ohms, resistor 204 allowsapproximately 2-3 amps to flow through the relay contacts 28, 30 whenthe AC line voltage reaches approximately 4-5 volts.

Current flow through resistor 204 is restricted to the positive halfcycle due to the blocking effect of diode 202. In addition, MOSFET 206can only turn on at a negative to positive zero crossing due to theaction of transistor 200. Resistors 192, 196 and diodes 202, 194 providebase current during the positive half cycle to effectively clamp thegate of MOSFET 206 to ground, preventing it from turning on. However,sufficient base current is not generated until the AC line voltagereaches approximately 4-5 volts. Thus, current is allowed to flowthrough resistor 204 until the AC line voltage reaches 4-5 volts,whereupon transistor 200 turns on, grounding the gate of MOSFET 206,effectively turning it off. Current flow through resistor 204 produces avoltage drop of approximately 10 mV across relay contacts 28, 30, forapproximately 250 μsec. The gate of MOSFET 206 is the source for theCURRENT₋₋ FLOW signal which is inverted before being ORed with the PWR₋₋ON₋₋ RESET bar signal by Or circuit 210.

If the device is properly wired to the AC power source while thecontacts are closed, voltage comparator 190 detects and amplifies thevoltage drop produced across the equivalent ohmic resistance 182 of therelay contact 28. Both sides of relay contact 28 are coupled to theinputs of voltage comparator 190 through 0.01 μF capacitors 186, 188.These capacitors provide isolation between the comparator's 190reference voltage and circuit ground. The voltage divider, consisting ofresistors 176 (10 MΩ), 178 (1 KΩ), 180 (2 MΩ), supplies the referencevoltage needed by comparator 190 to determine whether the IGFCI device10 is correctly wired. Resistors 181, 183 protect the inputs of thecomparator 190 when the relay contacts 28, 30 are in the "open" positionby limiting the current between the AC power source side and the loadside of the relay contacts 28, 30. Back to back diodes 187, 189 limitthe voltage potential between the amplifier inputs to a diode drop toprotect it against damage due to excessive voltage.

If the device is correctly wired, a positive pulse signal (i.e., a 12volt signal) appears at the output of comparator 190. This activelogical high signal, CONTACT₋₋ CURRENT, is clocked into latch circuit212 after first being gated with the CONTACT₋₋ CLOSED bar signal in Orcircuit 207. The "Q" output is an active low signal, MISWIRE₋₋ CLOSEDbar, and is only at a logical low when both relay contacts 28, 30 are inthe closed state, otherwise MISWIRE₋₋ CLOSED bar is high.

If MISWIRE₋₋ CLOSED bar is at a logical high, then the relay contacts28, 30 are open and the latch circuit input is at a logical high nomatter what the logical level of CONTACT₋₋ CURRENT signal. This is toassure that the circuit 212 output signal, MISWIRE₋₋ CLOSED bar, remainshigh in the event the relay contacts 28, 30 are in the open state inaccordance with open-contact miswiring detector 20 to determine whethera miswiring condition exists. The signal provided by Or circuit 210remains at a logical high level from the zero crossing until the ACreaches 4-5 volts. At that point, transistor 200 turns on and sinks thesignal at the gate of MOSFET 206 to ground, causing CURRENT₋₋ FLOW to golow. This signal is inverted by Nand circuit 208, the rising edge ofwhat is used to clock the level of CONTACT₋₋ CURRENT to the output oflatch circuit 212. The output, MISWIRE₋₋ CLOSED bar, is high if nomiswiring condition is sensed, and low, if a miswiring condition issensed.

If the device 10 were incorrectly wired (i.e., the AC power source wasconnected to the LOAD-1, LOAD-2 terminals), and the relay contacts 28,30 are closed, the current produced by resistor 204 would not flowthrough the contacts 28, 30. This is because the current path extendsfrom the LOAD-1 terminal through diode 202, resistor 204, MOSFET 206 tothe LOAD-2 terminal. Consequently, no current flows through relaycontacts 28, 30, which causes the output of comparator 190 to go low.The CONTACT₋₋ CLOSED signal is therefor driven low, since AC appears onboth sides of the relay contacts 28, 30. Correspondingly, when latchcircuit 212 is clocked, MISWIRE₋₋ CLOSED bar goes low, triggering thealarm, alerting the user that the device 10 is incorrectly wired andcausing the relay contacts 28, 30 to be tripped by the optocoupler 248(FIG. 7).

A preferred embodiment of a GFCI circuit 12, described broadly above inrelation to FIG. 1, will now be described with reference to FIG. 7.IGFCI terminals AC-1 and AC-2 are electrically connectable to phase andneutral lines of the AC source and to GFCI phase and neutral lineterminals AC-1₋₋ IN and AC-2₋₋ IN. A first or phase conducting element211 connects terminal AC-1 IN to terminal AC-1₋₋ OUT, and a second orneutral conducting element 213 electrically connects terminal AC-2₋₋ INto terminal AC-2₋₋ OUT. Terminals AC-1₋₋ OUT and AC-2₋₋ OUT are alsoelectrically connected to line sides of contacts 28, 30, respectively.Conducting elements 211 and 213 are positioned such that they extendthrough a pair of magnetic cores 312, 314 which sense AC flowing intoand out of the IGFCI device 10.

Terminal AC-1₋₋ OUT also is electrically connected to a first end ofrelay coil 260; a second end of relay coil 260 is electrically connectedto an anode end of a diode 252 and a cathode end of diode 256, whichtogether with diodes 254, 258, form a portion of a diode bridge. Cathodeends of diodes 252, 254 are electrically connected to an anode end of anSCR 244. The cathode end of SCR 244 is connected to a first end of aresistor 246, a second end of which is connected to floating ground, aswell as to an emitter gate of a transistor 249 of an optoelectronicswitch 248. Anode end of SCR 244 also is electrically connected to afirst end of a resistor 242 and a collector of transistor 249 of switch248.

Magnetic core 312 generates a signal AGC₋₋ IN which is proportional toan amount of current flowing into the GFCI and provides the signal asinput to pins 2 and 3 of the LM1851 228; the AGC₋₋ IN signal is alsoprovided to the automatic gain control (AGC) circuit 16 (FIG. 8).Magnetic core 314 generates a signal which is proportional to an amountof current flowing back from the GFCI (in the neutral) and provides thesignal across a capacitor 226. A first end of capacitor 226 is alsoconnected to a second end of a capacitor 222 as input to pin 4 of theLM1851 and to anode ends of diodes 256, 258. A second end of capacitor226 is electrically connected to pin 5 of LM1851 228.

The LM1851 228 is an integrated circuit which, via its input pins,detects small differences in the current flowing through the AC-1 andAC-2 terminals, identifying ground faults thereby. Upon detection of aground fault, the LM1851 228 conveys the fault information via the stateof a signal, GFCI₋₋ OUT, provided at pin 1. Pin 1 is electricallyconnected to a first end of a resistor 230, a second end of which isconnected to a first end of a capacitor 240 and a gate of an SCR 244.The state of the pin 1 output (i.e., signal GFCI₋₋ OUT) controls thestate of SCR 244 by integrating the GFCI output. In other words, aparticular level at capacitor 240, referred to as the SCR₋₋ GATE signal,controls the impedance state of the SCR. SCR₋₋ GATE defines the state ofconduction within the SCR path to ground, which in turn defines thecurrent flow from terminal AC-1 through conductive element 211, throughthe relay coil 260, diode 252, the conducting path of SCR 244, andresister 246; the neutral line current flows through diode 258, element213 to AC-2. Current flow through the coil 260 forces the relay contacts28, 30 to an open state, cutting off power to the load and preventing auser from being injured.

AGC circuit 16 (FIG. 8) is electrically connected to the GFCI 12 acrossfirst and second ends of a resister 232, preferably having a value ofaround 2 MΩ. The signal output from the AGC circuit across resistor 232,varies the sensitivity of the LM1851 228 to leakage current detected inthe system. A first end of resistor 232 also is electrically connectedto pins 8 and 6 of the LM185 1, and the resistor's second end isconnected to pin 8, a cathode end of a diode 234 and an anode end of astorage capacitor 236. Pin 7 of the LM1851 is electrically connectedacross a capacitor 238 to floating ground.

As mentioned above, SCR₋₋ GATE controls current flow through SCR 224,and the collector and emitter of transistor 249 of optocoupler 248 isconnected across the anode and cathode ends of SCR 244. The optocoupleris responsive to an ALARM₋₋ TRIP signal, generated within the alarmcircuitry 18, and provided at photodiode 251. When ALARM₋₋ TRIP goeshigh, i.e., an alarm condition occurs, current flows through thephotodiode to ground through resistor 250. This causes the optocouplerto turn on creating an alternate path for current which bypasses the SCRand energizes the coil 260 thereby opening relay contacts 28, 30. Thus,the optocoupler serves as a backup or alternate means of tripping therelay contacts 28, 30, either when the SCR has failed or when a failurein the GFCI 12 circuitry has been detected.

Another key feature of the system 10 of this invention is its ability todynamically adjust the leakage-current sensitivity of the GFCI circuit12 using automatic gain control (AGC). Currently, certain appliances arenot required to be protected by a GFCI because they generate undesirableparasitic ground leakage current that would interfere with the normaloperation of a GFCI. Appliances such as refrigerators, dishwashers,washing machines, etc. or devices with switching power supplies in them,for example, typically use capacitors in their filter circuits. Thesecapacitors usually are connected directly to the ground wire of the ACpower line, thus generating ground leakage and causing "nuisancetripping" of the GFCI. Because the IGFCI of this invention overcomes theproblems associated with such appliances, it is foreseen that IGFCIswill become a UL requirement within the same.

A preferred embodiment of an automatic gain control (AGC) circuit 16,described broadly above with reference to FIG. 1, will now be describedwith reference to FIG. 8. The AGC circuit 16 detects and compensates forslow rising, steady and fast rising leakage current. In other words, theAGC circuit distinguishes between fast rising leakage current caused bya human and steady or slowly rising leakage current caused by certainappliances or other devices. In a case where the leakage currentsteadily increases, the GFCI tracks this increase and raises itsinternal reference threshold level for tripping, above which anadditional 5 ma will trip the GFCI. In a case of steady state or slowlyrising leakage current, up to 25 ma can be compensated for by the AGCcircuit 16. However, any leakage current above 30 ma will trip the GFCI.Although the quiescent or steady state sensitivity can increase, theGFCI's dynamic sensitivity does not change. At all times, 5 ma of fastrising leakage (i.e., that produced by human contact) will trip the GFCIcircuit 12.

In order to receive the AGC₋₋ IN signal from the GFCI 12, first ends ofcapacitors 340, 342 are coupled to GFCI core 312. The capacitors preventthe circuit 16 from interfering with current sensing by the GFCI 12.Second ends of capacitors 344 and 346 are electrically connected tofirst ends of resistors 344, 346, the second ends of which areelectrically connected to inverting and non-inverting inputs to op-amp349, respectively. The second end of capacitor 342 also is electricallyconnected through a resistor 348 to 1/2 Vcc. An output of op-amp 349 iselectrically connected to cathode end of diode 350, an anode end ofwhich is connected to ground, and an anode end of diode 352.

Cathode end of diode 352 is electrically connected to a first end of acapacitor 362, a first end of a resistor 358, a second end of which isconnected to ground, a first end of a resistor 356 and a cathode end ofdiode 354. Anode end of diode 354 is electrically connected to a firstend of a capacitor 360, a second end of which is grounded, and to afirst end of a resistor 368. A second end of capacitor 362 iselectrically connected to a base of NPN transistor 366 and to a firstend of resistor 364, a second end of which is connected to ground. Anemitter of transistor 366 grounded while its collector is connected to asecond end of resistor 368, a first end of resistor 280, a second end ofwhich is grounded, and a base of transistor 286. An emitter oftransistor 286 is connected across a resistor 286 to ground and acollector is connected across a resistor 284 to a gate of FET 290.Second end of resistor 284 is also electrically connected to a first endof a transistor 282. A second end of resistor 282 is electricallyconnected to a first end of a 500 Kohm resistor 292, a second end ofwhich connects to a source of N-channel FET 292.

The signal output of amplifier 349 is rectified by diodes 350, 352, andcharges capacitor 360 through resistor 356. The voltage that appearsacross the capacitor 360 biases the base of transistor 286 throughresistors 368, 280. Collector current flowing through transistor 286causes the equivalent impedance of FET 290 to decrease. The FET/500 Kohmresistor 292 series combination is electrically connected in parallelwith the 2 MΩ threshold set resistor 232 (FIG. 7). Lowering theequivalent impedance (2 MΩ) by a factor of 5 corresponds to lowering thesensitivity of the GFCI to 25 ma. As the impedance decreases, so doesthe sensitivity. Consequently, it takes more current to trip the GFCI12, i.e., the steady state reference threshold at which the GFCI willtrip. For example, a steady leakage current of 1 ma causes the impedanceof the FET 290 to decrease so as to raise the leakage level at which theGFCI trips to 6 ma (i.e., 1 ma steady state threshold plus 5 ma fixeddynamic threshold). A steady state leakage of 5 ma will set the FET 290to an equivalent impedance of 1.5 MΩ. The resulting impedance sets thesensitivity of the GFCI to 10 ma (i.e., 5 ma steady state threshold plusfixed 5 ma dynamic threshold). The maximum equivalent impedance of theFET 290 will raise the steady state threshold to 25 ma. Thus, anyleakage over 30 ma will trip the GFCI.

Similarly, a slowly decreasing leakage current changes the steady statethreshold, above which 5 ma will trip the GFCI. A decreasing leakagecurrent causes the output of the amplifier 349 to decrease, reversebiasing diode 352. The accumulated charge on capacitor 360 dischargesthrough resistors 356, 358 to ground until it reaches the new level setby the output of amplifier 349. The drop in voltage across capacitor 360causes a corresponding increase in the impedance of the FET 290, theresult of the decreased collector current flowing through transistor286. This causes a higher voltage to appear at the gate of FET 290. Thishigher gate voltage raises the equivalent impedance of the FET 290. Thehigher resistance combined with set resistor 232, in parallel with theseries combination of FET 290 and resistor 292, lowers the GFCI circuit12 threshold.

As discussed earlier, the dynamic threshold of the GFCI 12 never changesfrom its preset level of 5 ma. Thus, if, for example, the steady statethreshold has risen from 0 ma to 10 ma due to 10 ma of leakage currentpresent on the AC power line, the device 10 would trip on 5 ma of fastrising leakage current, the type caused by humans. To accomplish this,the GFCI circuit 12 uses transistor 366 to quickly discharge capacitor360 and the base of transistor 286. This causes the equivalent impedanceof the FET 290 to revert back to its original 5 ma sensitivity setting.Fast rising leakage current of the type that could be caused by humanscauses the output of amplifier 349 to rise quickly causing current tocharge capacitor 362. The voltage across resistor 364 rises with risingcapacitor voltage until sufficient to turn on transistor 366. Transistor366 turning on quickly depletes the charge on the base of transistor286, turning it off and also quickly discharges capacitor 360.

Another important feature of IGFCI device 10 is the device's ability toconstantly monitor the GFCI circuitry 12 to assure proper operation inits task to protect users against ground faults. To accomplish thistask, a test circuit 14 is included to perform a built in test toperform two independent self test operations on the GFCI ensure usersafety. A first self test is performed once every hour and checks thatthe trip coil 260 and the SCR 244 are working properly. A second test isperformed once every two hours and checks that the GFCI IC 228 isworking properly. First and second self test circuits will now bedescribed with reference to FIGS. 9A, 9B, respectively.

Referring now to FIG. 9A, a preferred embodiment of a first portion ofself test circuit 14 for implementation within the present inventionwill be described. The first self test portion is electrically connectedto GFCI 12 within which the coil 260 and SCR 244 are tested inconjunction with the 1 HR₋₋ PULSE bar signal produced by the timingsignal generator 22. Consequently, the SCR 244 is turned on by SCR₋₋GATE near the end of the positive portion of the AC cycle, i.e., atapproximately 170 degrees. The presence of any current flowing throughthe SCR 244 is detected and identified by way of the SCR₋₋ CURRENTsignal. If no current is detected, the alarm is triggered and the relayswitches 28, 30 are tripped by the alternate trigger means ofoptocoupler 248 (described above).

LOAD-1 terminal is electrically connected to a first end of a resistor372 and a cathode end of a diode 370. Anode end of diode 370 iselectrically connected to second end of resistor 372, an anode end ofcapacitor 374, a cathode end of a zener diode 376 and two inputs of alogical Nand circuit 378 as a 170 degree sensitive signal, 170₋₋ DEG.The 170₋₋ DEG signal is generated through the resister 372 and capacitor374 pair during the positive half cycle when capacitor 374 chargesthrough resistor 372. The values are chosen so that the input to gate ofcircuit 378 rises high enough to cause its output to go low atapproximately 170 degrees into the positive half cycle, generating the170₋₋ DEG bar signal. Zener diode 376 simply prevents the input voltagefrom rising high enough to damage the gate inputs of Nand circuit 378.The output of gate circuit 378 (170₋₋ DEG bar) is a normally high signalthat goes low 170 degrees into the positive half cycle of the AC andremains low up to the zero crossing.

The 1 HR₋₋ PILSE signal generated within timing signal generator 22 iscombined with the 170₋₋ DEG signal within a logical Nor circuit 380, anoutput of which is provided to a base of a transistor 384. A collectorof transistor 384 is connected through resistor 382 to Vcc and thetransistor's emitter is connected t0 ground through a resistor 386.Thus, transistor 384 only turns on when both inputs to gate 380 are low.As mentioned earlier, the 1 HR₋₋ PULSE signal is approximately 75 mslong, straddling more than one cycle of the AC power. Current flowingthrough transistor 384 produces a voltage across resistor 386, turningon the SCR for approximately the final 10 degrees in the positive AChalf cycle. During the negative half cycle, diode 370 quickly dischargescapacitor 374 for the following positive half cycle.

If the trip coil 260 and the SCR 244 are functioning properly, currentwill flow through both of these components when transistor 384 turns on.It is at this point that the SCR₋₋ CURRENT signal, shown in FIG. 7, willbe at its maximum. This signal is provided to a pair of inputs to alogical Nand circuit 390, where it is inverted to generate SCR₋₋ CURRENTbar, and to a cathode end of a zener diode 388. SCR₋₋ CURRENT barpresets a latch circuit 392 causing the latch circuit's "Q" output toimmediately go high. 170₋₋ DEG bar and 1 HR₋₋ PULSE signals are input tological Or circuit 394, an output of which is provided to clock latchcircuits 392, 396. A "Q" output of latch circuit 392 is electricallyconnected as a D input to latch circuit 396; PWR₋₋ ON₋₋ RESET bar isprovided as its "preset" as well as to a "set" input of latch circuit392. Consequently, the rising edge of the 170₋₋ DEG bar clocks thelogical output of latch circuit 392 into latch circuit 396. Previously,upon power up, latch circuit 392 is reset low and latch circuit 396 isreset high. If current flows through the SCR 244, then a high is clockedinto latch circuit 396 and the output, SCR₋₋ FAIL bar, remains high. Thealarm, therefore, is not triggered. However, if no current is detected,then a low is clocked into latch circuit 396 and the SCR₋₋ FAIL barsignal goes low, the alarm is triggered and the relays 28, 30 aretripped by the optocoupler 248. Since the input to latch circuit 392 istied low, a low is always clocked from the latch circuit 392 Q output.Thus, in the absence of the preset pulse derived from SCR 244 current,latch circuit Q output defaults to a low, indicating a failure with theSCR 244 and/or the coil 260.

Referring now to FIG. 9B, a preferred embodiment of a second portion ofself test circuit 14 will be described. The 2 HR₋₋ PULSE signalgenerated within timing signal generator 22 is provided to the clockinput to a latch circuit 410. The clock input is also electricallyconnected to a first end of resistors 398, 498. A second end of resistor398 is electrically connected to a base of NPN transistor 400, anemitter of which is grounded and a collector of which provides a pathout for the SCR₋₋ GATE signal. A second end of resistor 408 iselectrically connected to a gate of N-channel FET 406. A source of FET406 is electrically connected to terminal AC-2₋₋ OUT, a drain of whichis electrically connected to a cathode end of a diode 404. An anode endof diode 404 is connected to terminal LOAD-1 through a resistor 402.GFCI₋₋ OUT and PWR₋₋ ON₋₋ RESET are provided as "D" and "preset" inputsto latch circuit 410, respectively.

The second self test is preferably performed every two hours and checksfor the proper operation ofthe LM1851 timer 114 and the GFCI 12,utilizing the 2 HR₋₋ PULSE signal produced by the timing signalgenerator 22. The 2 HR-PULSE signal activates FET 406 to simultaneouslysimulate a ground fault, prevent the SCR 244 from firing and detect theoutput of the GFCI 12. The high state of the 2 HR₋₋ PULSE signal turnson transistor 400 through resister 398, clamping the gate of the SCR 244to ground, and activates n-channel FET 406 through resistor 408,allowing current to flow during the positive half cycle from the LOAD-1terminal to the AC-2₋₋ OUT terminal through resistor 402 and diode 404,creating an imbalance in the current flowing through the magnetic cores312, 314. If the GFCI 12 is working properly, it will detect theimbalance created by the simulated ground fault and output a pulse onpin 1 (GFCI₋₋ OUT) of the timer 228.

The GFCI₋₋ OUT signal is input to the latch circuit 410 whereby a risingedge of the 2 HR₋₋ PULSE bar signal clocks it into the latch circuit asits "D" input. In consequence, the circuit's "Q" output, GFCI₋₋ FAIL barremains high (if operation was proper). However, if the GFCI₋₋ OUTsignal is low, the GFCI₋₋ FAIL bar signal goes low, triggering the alarmand tripping the relay contacts 28, 30 through the optocoupler 248. The"Q" output of the latch 410 is normally high, being preset high by thePWR₋₋ ON₋₋ RESET bar signal upon initial application of the AC power.The SCR is prevented from firing during the test by the clamping actionof transistor 400. The gate of SCR 244 is held close to ground potentialby transistor 244 preventing SCR 244 from turning on while the test isin progress. In other words, no response to the simulated ground faultis utilized by the test.

It should be noted that as defined herein, slowly rising leakage currentis defined as that leakage current typically associated with certainappliances such as washers, dishwashers, etc. Quickly changing leakagecurrent is identified as such changes in current that are indicative ofa ground fault, e.g., greater than 5 ma. for a set time period.

The embodiments of the invention disclosed in the present specification,drawings and claims are presented merely as examples of the invention.Other embodiments, forms, or modifications thereof will readily suggestthemselves and are contemplated as coming within the scope of thepresent invention.

What is claimed is:
 1. An intelligent circuit interrupt systemelectrically connected load upon detection of an interrupt condition,comprising:circuit interrupt means including line and load side phaseand neutral ports, wherein said line side phase and neutral ports areelectrically connected, respectively, to phase and neutral terminals ofsaid AC source and said circuit interrupt mean generate an interruptsignal for interrupting said AC flow at detection of said interruptcondition; a relay switch including a relay coil and phase and neutralcontacts, wherein line and load ends of said phase contact areelectrically connected, respectively, between said interrupt means loadside phase port and a phase terminal of said load, line and load ends ofsaid neutral contact are electrically connected, respectively, betweensaid interrupt means load side neutral port and a neutral terminal ofsaid load and said relay coil is electrically coupled between said loadends of said phase and neutral contacts for controlling said contacts inresponse to said interrupt signal; an open-contact miswiring detector(OCMD) electrically connected to said line and load ends of one of saidphase and neutral contacts for detecting a miswiring condition when saidcontacts are in an open state; a closed-contact miswiring detector(CCMD) electrically connected to said load end of said phase contact andto said line and load ends of one of said neutral and phase contacts fordetecting a miswiring condition when said contacts are in a closedstate; a timing signal generator electrically connected to said open andclosed contact miswiring detectors for generating system timing signals;a test circuit electrically coupled to said interrupt means andresponsive to said timing signal generator for regularly testing saidinterrupt means' operability; an alarm circuit electrically responsiveto each of: said test circuit, said timing signal generator, said opencontact miswiring detector and said closed contact miswiring detectorfor communicating at least one of: an open-contact miswiring condition,a closed-contact miswiring condition, an operational failure condition,and a need for external testing condition; and a power supplyelectrically connected between said load ends of said phase and neutralcontacts, and to said timing signal generator.
 2. The intelligentcircuit interrupt system defined by claim 1, wherein said interruptcircuit monitors a line current flowing from said source to said loadand a neutral current flowing from said load to said source, andgenerates said interrupt signal based on a detected difference betweensaid line and neutral currents.
 3. The intelligent circuit interruptersystem defined by claim 1, wherein said circuit interrupt meanscomprises a ground fault interrupt circuit.
 4. The intelligent circuitinterrupter system defined by claim 1, wherein said interrupt signalcauses said relay coil to trip said relay contacts to an open state. 5.The intelligent circuit interrupter system defined by claim 1, whereinsaid miswiring conditions arise from a detection of one of said ACsource phase and neutral terminals electrically connected, respectively,to one of said load ends of said phase and neutral contacts.
 6. Theintelligent circuit interrupter system as defined by claim 1, whereinsaid alarm circuit includes a piezoelectric transducer for generating atleast one frequency-dependent alarm signal.
 7. The intelligent circuitinterrupter system as defined by claim 1, wherein said test circuitimplements a self test at least every 2 hours.
 8. The intelligentcircuit interrupt system defined by claim 1, further including a surgesuppressor electrically connected across said interrupt means line sidephase and neutral ports.
 9. The intelligent interrupter system asdefined by claim 8, wherein said surge suppressor includes a metal oxidevaristor.
 10. The intelligent circuit interrupter system defined byclaim 1, wherein said alarm circuit indicates a need for a user to testsaid system at least every 30 days.
 11. The intelligent circuitinterrupt system of claim 10, wherein said alarm circuit regularlycommunicates said need to test said system pursuant to said need to testindication until said system is tested by said user, except during otherthan daylight hours.
 12. The intelligent circuit interrupt systemdefined by claim 1, further including automatic gain control meanselectrically coupled to said interrupt means for providing an adjustsignal to said circuit interrupt means to vary a definition of saidinterrupt condition.
 13. The intelligent circuit interrupt systemdefined by claim 12, wherein said automatic gain control means tracksand defines leakage current losses within said system and automaticallyadjusts said adjust signal to compensate therefor.
 14. The intelligentcircuit interrupt system defined by claim 13, wherein automatic gaincontrol means adjusts for slowly varying leakage currents of try to 25ma.
 15. The intelligent circuit interrupt system defined by claim 13,wherein said interrupt signal interrupts said flow of AC at detection ofa leakage current of at least 5 ma. determined to have changed abruptly.16. A method of detecting ground faults at a load side of an interruptcircuit electrically connected between an AC source and a load such thatAC flowing through said circuit is reliably interrupted upon detectionof an interrupt condition by said circuit, comprising the stepsof:detecting a first mount of AC flowing from said AC source to saidload utilizing said interrupt circuit; detecting a second amount of ACflowing from said load to said AC source utilizing said interruptcircuit; generating a difference signal indicative of a differencebetween said first and second amounts; comparing said difference signalto a reference signal which is proportional to a maximum AC flowdifference to define an interrupt condition in response thereto;interrupting said flow of AC upon occurrence of said condition;monitoring said circuit and identifying alarm conditions which requireuser intervention to assure reliable ground fault detection; whereinsaid alarm conditions are determined on occurrence of an interruptcircuit miswiring detection, a detection of an inoperative conditionwithin said interrupt circuit and a detection of a time which requiresuser assistance in testing said interrupt circuit operability; andgenerating an alarm signal appropriate for communicating to a user aneed for said intervention.
 17. A method of detecting ground faults at aload side of an interrupt circuit electrically connected between an ACsource and a load such hat AC flowing through said circuit is reliablyinterrupted upon detection of an interrupt condition by said circuit,comprising the steps of:detecting a first amount of AC flowing from saidAC source to said load utilizing said interrupt circuit; detecting asecond amount of AC flowing from said load to said AC source utilizingsaid interrupt circuit; generating a difference signal indicative of adifference between said first and second amounts; comparing in acomparator said difference signal to a reference signal which isproportional to a maximum AC flow difference to define an interruptcondition in response thereto; interrupting said flow of AC uponoccurrence of said condition; monitoring said circuit and identifyingalarm conditions which require user intervention to assure reliableground fault detection; generating an alarm signal appropriate forcommunicating to a user a need for said intervention, wherein said alarmconditions are determined on occurrence of an interrupt circuitmiswiring detection, a detection of an inoperative condition within saidinterrupt circuit and a detection of a time which requires userassistance in testing said interrupt circuit operability; generating analarm signal appropriate for communicating to a user a need for saidintervention; and adjusting a sensitivity of said comparator inaccordance with non-alarm condition leakage current detection, includinga comparison of a detected rate of change of leakage current determinedduring said step of comparing.